An R-2R circuit is a simple and inexpensive way to perform digital-to-analog conversion that typically uses arrangements of precision resistor networks in a ladder-like configuration. FIG. 1A shows a basic R-2R resistor ladder for an N-bit digital to analog conversion, where a0-a(N−1) are the N bits from the least to the most significant, are converted to a corresponding analog value at the output. To effect a conversion, the bits are switched between ground (“0”) and Vref (“1”) based on the N digital input for the 2N possible output values. FIGS. 1b and 1c show variations, respectively in 3 bit and 6 bit variations.
Although the sort of R-2R ladder shown in FIG. 1a is inexpensive and relatively easy to manufacture, since only two resistor values are required, it is subject to inaccuracies such as differential non-linearity. The R-2R ladder operates as a string of current dividers whose output accuracy is dependent on how well each resistor is matched to the others. Small inaccuracies in the more significant bits' resistors can overwhelm the contribution of the less significant bits, resulting in particularly non-linear differential behavior at major crossings, such as from 01111 . . . to 10000 . . . . This can limit the accuracy and usefulness of such circuits for DAC conversion involving high numbers of bits. Referring back to FIG. 1a, at such a transition, although the value may only change by one, the values of all or almost all bits are flipped. This effect is illustrated schematically in FIGS. 2a and 2b, where the higher bit transitions, such as at 511 (where a9 switches from 0 to 1) or 255 (where a8 switches), typically result in a non-linear incremental increase. Depending on the specific case these kinks in the step size can either be positive, as in FIG. 2a, or negative, as in FIG. 2b, or mixed (positive at MSB and negative at the next most significant bit, for example).
Digital to Analog Converters (DACs) based on an R-2R circuit are often employed as peripheral elements on larger circuits. One example is for supplying the various read voltages used on multi-level non-volatile memory circuits. (Examples of such non-volatile memory circuits are presented in US patent application publication number US-2008-0019188-A.) FIGS. 3a and 3b are experimental data to show the behavior of one such actual circuit over a sub-range of the digital input. As shown in FIG. 3a, a digital value along the horizontal axis is converted into an analog value (VCGRV, corresponding to a control gate read voltage value) ranging from 0V to 3V, as shown on the vertical axis. The behavior is generally increasing, but not quite linear. The non-linearity is more apparent in FIG. 3b, which shows the incremental step size plotted against the digital input value. Particularly prominent kinks occur at decimal values 108 and 236, corresponding to higher order bit transitions. Consequently, there is room for improvement in the behavior of such circuits.